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  ht48r01/HT48R02/ht48r03 10-pin msop i/o type 8-bit otp mcu selection table part no. vdd program memory data memory i/o timer external interrupt buzzer stack package types ht48r01 2.2v~5.5v 1k  14 64  8 7 i/o, 1 input 8-bit  1 1  4 10msop HT48R02 2.2v~5.5v 2k  14 96  8 7 i/o, 1 input 8-bit  2 1  6 10msop ht48r03 2.2v~5.5v 4k  15 160  8 7 i/o, 1 input 8-bit  2 1  8 10msop rev. 1.00 1 december 20, 2006 general description the ht48r01/HT48R02/ht48r03 are 8-bit high per - formance, risc architecture microcontroller devices specifically designed for i/o control. the advantages of low power consumption, i/o flexibil - ity, timer functions, oscillator options, power-down and wake-up functions, watchdog timer, buzzer driver, as well as low cost, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem con - trollers, etc. features  operating voltage: f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v f sys =12mhz: 4.5v~5.5v  7 bidirectional i/o lines and 1 input  interrupt input shared with i/o line  4 oscillator configuration options  external crystal osc  external rc osc  internal rc+i/o (pa5, pa6)  internal rc+rtc osc (32768hz)  internal rc oscillator  3 frequency selections: 4mhz/8mhz/12mhz  4mhz with  10% variation (2.2v~5.5v, 25  c)  8mhz with  10% variation (3.3v~5.5v, 25  c)  12mhz with  10% variation (4.5v~5.5v, 25  c)  watchdog timer  program memory rom: up to 4096  15  data memory ram: up to 160  8  buzzer driving pair and pfd supported  power-down and wake-up functions reduce power consumption  up to 0.5  s instruction cycle with 8mhz system clock at v dd =5v  all instructions executed within one or two machine cycles  14-bit or 15-bit table read instruction  up to 8-levels of subroutine nesting  bit manipulation instruction  low voltage reset function  10-pin msop package technical document  tools information  faqs  application note  ha0003e communicating between the ht48 & ht46 series mcus and the ht93lc46 eeprom  ha0016e writing and reading to the ht24 eeprom with the ht48 mcu series  ha0018e controlling the ht1621 lcd controller with the ht48 mcu series  ha0049e read and write control of the ht1380
block diagram pin assignment ht48r01/HT48R02/ht48r03 rev. 1.00 2 december 20, 2006        

                 
              
       
   
                                          !        "  #  $          %            & '    " (  

  )        * ' 
' 
  +  , (   (     '  -        *     . / 0   0   0
     *   $ 1        0    
  0  . /    . /      0          2      )  
  +  
  3   , $ 1  2    
' 
. /    
$ 1  2     2      -   ' 
            
             0    . /   0  . / (   2   )  
  +  
  3   , (   0 ' ' 4 ' ' 5 ' ' 3 ' ' +  2 )             0    . /   0  . / (   2      )  
  +  
  3   , (   0 ' ' 4 ' ' 5 ' ' 3 ' ' +  2 )                     

pin description pin name i/o configura - tion options description pa0/bz pa1/bz i/o  bidirectional 2-line i/o. each pin can be setup as a wake-up input using a soft - ware register. software instructions determine if each pin is a cmos output or a schmitt trigger input. pull-high resistors can be connected using a pull-high soft - ware register. pa0/pa1 are pin-shared with the bz and bz buzzer function pins. pa2/tmr0 i/o  bidirectional single line i/o. pa2 can be setup as a wake-up input using a soft - ware register. software instructions determine if the pin is a cmos output or schmitt trigger input. a pull-high resistor can be connected using a pull-high soft - ware register. this line is pin-shared with the timer/event 0 counter input. pa3/int i/o  bidirectional single line i/o. pa3 can be setup as a wake-up input using a soft - ware register. software instructions determine if the pin is a cmos output or schmitt trigger input. a pull-high resistor can be connected using a pull-high soft - ware register. this line is pin-shared with int . pa4/tmr1 i/o  bidirectional single line i/o. pa4 can be setup as a wake-up input using a soft - ware register. software instructions determine if the pin is a cmos output or schmitt trigger input. a pull-high resistor can be connected using a pull-high soft - ware register. this line is pin-shared with the timer/event counter 1 input. osc1/pa6 osc2/pa5 i/o rc, crystal, rtc or i/o bidirectional 2-line i/o and oscillator pins. if configured as i/os, software instruc - tions determine if each pin is a cmos output or a schmitt trigger input. pull-high resistors can be connected using a pull-high software register. a configuration option determines the choice of oscillator mode and i/o function. the four oscilla - tor modes are: 1. internal rc osc: both pins configured as i/os 2. external crystal osc: both pins configured as osc1/osc2 3. internal rc + rtc osc: both pins configured as osc2, osc1. 4. external rc osc+pa5: pa6 configured as osc1 pin, pa5 configured as i/o note: when the system clock is sourced from the internal rc osc, there are 3 frequency options 12mhz, 8mhz and 4mhz. pa7/res i pa7 or res active low schmitt trigger reset input or pa7 input. vdd  positive power supply vss  negative power supply, ground * all pull-high resistors are controlled by an register option bit. absolute maximum ratings supply voltage ...........................v ss  0.3v to v ss +6.0v storage temperature ............................  50  cto125  c input voltage..............................v ss  0.3v to v dd +0.3v operating temperature...........................  40  cto85  c i ol total ..............................................................150ma i oh total............................................................  100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under
absolute maximum ratings
may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. ht48r01/HT48R02/ht48r03 rev. 1.00 3 december 20, 2006
d.c. characteristics ta=25  c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage  f sys =4mhz 2.2  5.5 v  f sys =8mhz 3.3  5.5 v  f sys =12mhz 4.5  5.5 v i dd1 operating current (crystal osc, rc osc) 3v no load, f sys =4mhz  12ma 5v  2.5 5 ma i dd2 operating current (crystal osc, rc osc) 3v no load, f sys =8mhz  24ma 5v  48ma i dd3 operating current (crystal osc, rc osc) 5v no load, f sys =12mhz  612ma i dd4 operating current (internal rc+rtc osc, normal mode) 3v no load, f sys =4mhz  12ma 5v  2.5 5 ma i dd5 operating current (internal rc+rtc osc, normal mode) 3v no load, f sys =8mhz  24ma 5v  48ma i dd6 operating current (internal rc+rtc osc, normal mode) 5v no load, f sys =12mhz  612ma i dd7 operating current (internal rc+rtc osc, slow mode) 3v no load, f sys =32768hz  10 20  a 5v  20 40  a i stb1 standby current (wdt enabled, rtc off) 3v no load, system halt  5  a 5v  10  a i stb2 standby current (wdt disabled, rtc off) 3v no load, system halt  1  a 5v  2  a i stb3 standby current (wdt disabled, rtc on) 3v no load, system halt  5  a 5v  10  a v il1 input low voltage for pa0~pa6, tmr0, tmr1 and int  0  0.3v dd v v ih1 input high voltage forpa0~pa6, tmr0, tmr1 and int  0.7v dd  v dd v v il2 input low voltage (pa7/res )  0  0.4v dd v v ih2 input high voltage (pa7/res )  0.9v dd  v dd v v lvr1 low voltage reset 1  configuration option: 4.2v 3.98 4.2 4.42 v v lvr2 low voltage reset 2  configuration option: 3.15v 2.98 3.15 3.32 v v lvr3 low voltage reset 3  configuration option: 2.1v 1.98 2.1 2.22 v i ol i/o port sink current 3v v ol =0.1v dd 48  ma 5v 10 20  ma i oh i/o port source current 3v v oh =0.9v dd  2  4  ma 5v  5  10  ma r ph pull-high resistance 3v  20 60 100 k 5v 10 30 50 k ht48r01/HT48R02/ht48r03 rev. 1.00 4 december 20, 2006
a.c. characteristics ta=25  c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc, rc osc)  2.2v~5.5v 400  4000 khz  3.3v~5.5v 400  8000 khz  4.5v~5.5v 400  12000 khz f sys2 system clock (internal rc osc) (  10%) 4.5v~ 5.5v 12mhz, ta=25  c 10800 12000 13200 khz 3.3v~ 5.5v 8mhz, ta=25  c 7200 8000 8800 khz 2.2v~ 5.5v 4mhz, ta=25  c 3600 4000 4400 khz f sys3 system clock (32768 crystal)   32768  hz f timer timer i/p frequency (tmr)  2.2v~5.5v 0  4000 khz  3.3v~5.5v 0  8000 khz  4.5v~5.5v 0  12000 khz t wdtosc watchdog oscillator period 3v  45 90 180  s 5v  32 65 130  s t res external reset low pulse width  1  s t sst system start-up timer period  wake-up from halt  1024  t sys t int interrupt pulse width  1  s t lvr low voltage width to reset  0.25 1 2 ms v por vdd start voltage to ensure power-on reset   100 mv r por vdd rise rate to ensure power-on reset  0.035  v/ms note: t sys =1/f sys1 , 1/f sys2 or 1/f sys3 ht48r01/HT48R02/ht48r03 rev. 1.00 5 december 20, 2006
ht48r01/HT48R02/ht48r03 rev. 1.00 6 december 20, 2006 functional description execution flow the system clock for the microcontroller is derived from either a crystal or an rc oscillator. the system clock is internally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute in a cycle. if an instruction changes the program counter, two cycles are required to complete the instruction. program counter  pc the program counter controls the sequence in which the instructions stored in program memory are executed and its contents specify the full range of program mem - ory. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call, initial re - set, internal interrupt, external interrupt or return from subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed with the next instruction. the lower byte of the program counter (pcl) is a read - able and writable register (06h). moving data into the pcl performs a short jump. the destination will be within 256 locations. when a control transfer takes place, an additional dummy cycle is required.      2      2      2 6    # '    ' 7 
8 , 9      '    ' 7 
: 8 6    # '    ' 7 
; 8 , 9      '    ' 7 
8 6    # '    ' 7 
; 8 , 9      '    ' 7 
; 8 

; 
;     '
*   < 
' 7 
'   *  8 
execution flow mode program counter *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 000000000000 external interrupt 000000000100 timer/event counter overflow 000000001000 skip program counter+2 loading pcl *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *11~*0: program counter bits s11~s0: stack register bits #11~#0: instruction code bits @7~@0: pcl bits for ht48r01, the program counter is 10 bits wide, i.e. from *9~*0 for HT48R02, the program counter is 11 bits wide, i.e. from *10~*0 for ht48r03, the program counter is 12 bits wide, i.e. from *11~*0
ht48r01/HT48R02/ht48r03 rev. 1.00 7 december 20, 2006 program memory  rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 1024  14 bits for the ht48r01, 2048  14 bits for the HT48R02 or 4096  15 bits for the ht48r03, addressed by the program counter and table pointer. certain locations in the program memory are reserved for special usage:  location 000h this area is reserved for program initialization. after chip reset, the program always begins execution at lo - cation 000h.  location 004h this area is reserved for the external interrupt service program. if the int input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004h.  location 008h this location is reserved for the timer/event counter 0 interrupt service program. if a timer interrupt results from a timer/event counter 0 overflow, and the inter - rupt is enabled and the stack is not full, the program begins execution at location 008h.  location 00ch (HT48R02/ht48r03 only) this location is reserved for the timer/event counter 1 interrupt service program. if a timer interrupt results from a timer/event counter 1 overflow, and the inter - rupt is enabled and the stack is not full, the program begins execution at location 00ch.  table location any location in the program memory can be used as look-up tables. the instructions
tabrdc [m]
(the current page) and
tabrdl [m]
(the last page) trans - fer the contents of the lower-order byte to the speci - fied data memory, and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the table is well-defined, the other bits of the table   =    '       *  >      '        , 9      * '          '  ?              , =    '
      ' 0 '          '  ?        ' "   < :   '   ? *  ' 7 ) + ' @   ! 8 "   < :   '   ? *  ' 7 ) + ' @   ! 8     a '  '      ' $    ' 0 '   '    =    '       *  >      '        , 9      * '          '  ?              , =    '
      ' 0 '          '  ?        ' "   < :   '   ? *  ' 7 ) + ' @   ! 8 "   < :   '   ? *  ' 7 ) + ' @   ! 8     a '  '      ' $    ' 0 '   ' 3       , =    '
      ' '          '  ?        '  0 0 b  6 6 b   =    '       *  >      '        , 9      * '          '  ?              , =    '
      ' 0 '          '  ?        ' "   < :   '   ? *  ' 7 ) + ' @   ! 8 "   < :   '   ? *  ' 7 ) + ' @   ! 8     a '  '      ' $    ' 0 '   ' 6 0 0 0 b 0 0 2 b 0 0 5 b 0 0
b 6 6 6 b 6 0 0 b       , =    '
      ' '          '  ?        '                      2 ' ?               2 ' ?   ) ' ?                6 6 b  6 6 b  0 0 b 0 0 0 b 0 0 2 b 0 0 5 b  0 0 b              0 0 b  6 6 b 0 0 0 b 0 0 2 b 0 0 5 b 0 0
b 3 6 6 b 3 0 0 b program memory instruction table location *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1111@7@6@5@4@3@2@1@0 table location note: *11~*0: table location bits p11~p8: current program counter bits @7~@0: table pointer bits for the ht48r01, the table address location is 10 bits, i.e. from *9~*0 for the HT48R02, the table address location is 11 bits, i.e. from *10~*0 for the ht48r03, the table address location is 12 bits, i.e. from *11~*0
ht48r01/HT48R02/ht48r03 rev. 1.00 8 december 20, 2006 word are transferred to the lower portion of tblh, and the remaining 2 bits are read as
0
. the table higher-order byte register (tblh) is read only. the ta - ble pointer (tblp) is a read/write register (07h), which indicates the table location. before accessing the table, the location must be placed in tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr, and errors may occur. therefore, using the table read instruction in the main routine and the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt is supposed to be disabled prior to the table read instruction. it will not be enabled until the tblh has been backed up. all table related instructions re - quire two cycles to complete the operation. these ar - eas may function as normal program memory depending upon the requirements. stack register  stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is or - ganised up to 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledgment, the con- tents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return ret or reti instruction, the program counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. when the stack pointer is decremented by ret or reti, the interrupt will be serviced. this feature prevents stack overflow allow - ing the programmer to use the structure more easily. in a similar case, if the stack is full and a
call
is subse - quently executed, a stack overflow occurs and the first entry will be los. only the most recent 4 return ad - dresses are stored. data memory  ram the data memory is divided into two functional groups: special function registers and general purpose data memory 64  8 for the ht48r01, 96  8 for the HT48R02 or 160  8 for the ht48r03. most are read/write, but some are read only. the unused space before 20h is reserved for future ex - panded usage and reading these locations will get
00h
. the general purpose data memory, addressed from 20h to 5fh (ht48r01), 20h to 7fh (HT48R02) or 20h to bfh (ht48r03), is used for data and control information under instruction commands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di - rectly. except for some dedicated bits, each bit in the data memory can be set and reset by
set [m].i
and
clr [m].i
. they are also indirectly accessible through memory pointer register (mp;01h). indirect addressing register location 00h/02h are indirect addressing registers that are not physically implemented. any read/write opera - tion of [00h]/[02h] accesses data memory pointed to by mp0 (01h)/mp1 (03h). reading location 00h itself indi - rectly will return the result 00h. writing indirectly results in no operation. the memory pointer registers (mp0/mp1) are 7-bit registers (ht48r01/HT48R02) or 8 bit registers (ht48r03). the bit 7 of mp0/mp1 (ht48r01/ HT48R02) are undefined and reading will return the result
1
. any writing operation to mp0/mp1 will only transfer the lower 7-bit data to mp. accumulator the accumulator is closely related to alu operations. it is also mapped to location 05h of the data memory and can carry out immediate data operations. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit  alu this circuit performs 8-bit arithmetic and logic opera - tions. the alu provides the following functions:  arithmetic operations (add, adc, sub, sbc, daa)  logic operations (and, or, xor, cpl)  rotation (rl, rr, rlc, rrc)  increment and decrement (inc, dec)  branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of data operations but also changes the status register.
ht48r01/HT48R02/ht48r03 rev. 1.00 9 december 20, 2006      * '           '      0 0 b 0 b 0 b 0  b 0 2 b 0 ) b 0 + b 0 3 b 0 5 b 0 4 b 0  b 0 . b 0
b 0  b 0 , b 0 6 b 0 b b b  b 2 b ) b + b 3 b 5 b 4 b  b . b
b  b , b 6 b a '     ! &    ! '  ' c 0 0 c %      * '           '      7 + 2 ' .    8 ) 6 b 0 b   !      '  ! !      '        ' 0  0   !      '  ! !      '        '  


"  . "   . " b -         
0   0   0
   
      - 
  " -
              * '           '      0 0 b 0 b 0 b 0  b 0 2 b 0 ) b 0 + b 0 3 b 0 5 b 0 4 b 0  b 0 . b 0
b 0  b 0 , b 0 6 b 0 b b b  b 2 b ) b + b 3 b 5 b 4 b  b . b
b  b , b 6 b a '     ! &    ! '  ' c 0 0 c %      * '           '      7 4 + ' .    8 3 6 b 0 b   !      '  ! !      '        ' 0  0   !      '  ! !      '        '  


"  . "   . " b -         
0   0   0
   
   
      - 
  " -
              * '           '      0 0 b 0 b 0 b 0  b 0 2 b 0 ) b 0 + b 0 3 b 0 5 b 0 4 b 0  b 0 . b 0
b 0  b 0 , b 0 6 b 0 b b b  b 2 b ) b + b 3 b 5 b 4 b  b . b
b  b , b 6 b a '     ! &    ! '  ' c 0 0 c %      * '           '      7 + 0 ' .    8 . 6 b 0 b   !      '  ! !      '        ' 0  0   !      '  ! !      '        '  


"  . "   . " b -         
0   0   0
   
   
      - 
  " -
         ram mapping status register  status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition opera- tions related to the status register may give different re- sults from those intended. the to flag can be affected only by system power-up, a wdt time-out or executing the
clr wdt
or
halt
instruction. the pdf flag can be affected only by executing the
halt
or
clr wdt
instruction or a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. bit no. label function 0 c c is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. 1 ac ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3 ov ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by system power-up or executing the
clr wdt
instruction. pdf is set by executing the
halt
instruction. 5 to to is cleared by system power-up or executing the
clr wdt
or
halt
instruction. to is set by a wdt time-out. 6~7  unused bit, read as
0
status (0ah) register
ht48r01/HT48R02/ht48r03 rev. 1.00 10 december 20, 2006 in addition, on entering the interrupt sequence or exe - cuting the subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status are important and if the subroutine can cor - rupt the status register, precautions must be taken to save it properly. system control register bit no. label function 0 clkmod clock mode selection - select the system clock source 0: high speed clock as system clock - internal rc 1: low speed clock as system clock - 32.768khz, and rc oscillator stop note: this selection is used only in internal rc + rtc mode. 1 qosc 32768hz osc quick start-up oscillating setting 0: quickly startup 1: slow startup 2 3 bzen0 bzen1 bz/bz enable/disable 00: both disabled 01: reserved 10: bz only enabled 11: bz and bz enabled when bz or bz are disabled, the i/o port will have general i/o functions. if enabled, the bz or bz outputs will still be controlled by the related i/o port control and data settings. refer to the i/o chapter for details. 4~5  unused bit, read as
0
6 bzcs bzcs, buzzer clock source, 0/1: timer0/timer1 7 unused bit, read as
0
ctrl (16h) register note: for the ht48r01, bzcs is always 0 no matter what value is written into it; i.e., clock source for buzzer is only from timer0. interrupt the device provides an external interrupt and internal timer/event counter interrupts. the interrupt control reg - ister (intc;0bh) contains the interrupt control bits to set the enable or disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked, by clearing the emi bit. this scheme may prevent any further interrupt nesting. other interrupt requests may happen during this interval but only the interrupt request flag is recorded. if a certain in - terrupt requires servicing within the service routine, the emi bit and the corresponding bit in the intc register may be set to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the sp is decre - mented. if immediate service is desired, the stack must be prevented from becoming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro - gram memory. only the program counter is pushed onto the stack. if the contents of the register or status register are altered by the interrupt service program which cor - rupts the desired control sequence, the contents should be saved in advance. external interrupts are triggered by a high to low transi - tion of int and the related interrupt request flag (eif; bit 4 of intc) will be set. when the interrupt is enabled, the stack is not full and the external interrupt is active, a sub - routine call to location 04h will occur. the interrupt re - quest flag (eif) and emi bits will be cleared to disable other interrupts.
ht48r01/HT48R02/ht48r03 rev. 1.00 11 december 20, 2006 the internal timer/event counter interrupt is initialised by setting the timer/event counter interrupt request flag (tf; bit 5 of intc), caused by a timer overflow. when the interrupt is enabled, the stack is not full and the tf bit is set, a subroutine call to location 08h will occur. the related interrupt request flag,tf, will be reset and the emi bit cleared to disable further interrupts. during the execution of an interrupt subroutine, other in - terrupt acknowledgments are held until the
reti
instruction is executed or the emi bit and the related in - terrupt control bit are set to 1 (of course, if the stack is not full). to return from the interrupt subroutine,
ret
or
reti
may be invoked. reti will set the emi bit to en - able an interrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 1 04h timer/event counter 0 overflow 2 08h interrupt subroutine vector for ht48r01 interrupt source priority vector external interrupt 1 04h timer/event counter 0 overflow 2 08h timer/event counter 1 overflow 3 0ch interrupt subroutine vector for HT48R02/ht48r03 once the interrupt request flags (t0f/ t1f, eif) are set, they will remain in the intc register until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the
call subroutine
within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well con - trolled, the original control sequence will be damaged once the
call
operates in the interrupt subroutine. oscillator configuration there are 4 different oscillator modes implemented in the microcontroller, which are selected by configuration options. all of them are designed for system clocks, namely the external rc oscillator (erc), external crys - tal oscillator (ecry), internal rc oscillator with i/o(irc) and internal rc oscillator with rtc osc (irc+rtc). no matter what oscillator type is selected, the signal provides the system clock. the power-down mode stops the system oscillator, except for the rtc oscilla- tor, and resists external signals to conserve power. bit no. label function 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 eei controls the external interrupt (1= enabled; 0= disabled) 2 et0i controls the timer/event counter 0 interrupt (1= enabled; 0= disabled) 3, 6~7  unused bit, read as
0
4 eif external interrupt request flag (1= active; 0= inactive) 5 t0f internal timer/event counter 0 request flag (1= active; 0= inactive) intc 0 (0bh) register for ht48r01 bit no. label function 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 eei controls the external interrupt (1= enabled; 0= disabled) 2 et0i controls the timer/event counter 0 interrupt (1= enabled; 0= disabled) 3 et1i controls the timer/event counter 1 interrupt (1= enabled; 0= disabled) 4 eif external interrupt request flag (1= active; 0= inactive) 5 t0f internal timer/event counter 0 request flag (1= active; 0= inactive) 5 t1f internal timer/event counter 1 request flag (1= active; 0= inactive) 7  unused bit, read as
0
intc 0 (0bh) register for HT48R02/ht48r03
ht48r01/HT48R02/ht48r03 rev. 1.00 12 december 20, 2006 if the configuration options select the irc+rtc, the de - vice supports two kinds of system clock. when com - bined with the power-down function, it forms three operation modes. the two kinds of system clock are in - ternal rc oscillator or rtc osc (32768hz) which is se - lected by the ctrl register clkmod bit. the three operation modes are named as normal, slow, or idle mode. the following tables shows their relationship. if an rc oscillator is used, an external resistor between osc1 and vdd is required whose resistance must range from 24k  to 1.5m  . the rc oscillator provides the most cost effective solution. the frequency of oscil - lation may vary with vdd, temperatures and the chip it - self due to process variations. it is, therefore, not suitable for timing sensitive operations where an accu - rate oscillator frequency is desired. if the crystal oscillator is used, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are demanded. instead of a crystal, a reso - nator can also be connected between osc1 and osc2 to obtain a frequency reference, but two external capaci - tors connected to osc1 and osc2 are required. if an internal rc oscillator is used, osc1 and osc2 can be selected as general i/o lines or as a 32768hz crystal (rtc) oscillator. the frequencies of internal oscillator can be 12mhz, 8mhz and 4mhz which is selected by configuration options. the wdt oscillator is a free running on-chip rc oscilla- tor, and no external components are required. even if the system enters the power down mode, the system clock is stopped, but the wdt oscillator still works with a period of approximately 65  s at 5v. the wdt oscillator can be disabled by configuration options to conserve power. watchdog timer  wdt the wdt clock source may come from a dedicated rc oscillator (wdt oscillator), rtc clock or instruction clock (system clock divided by 4) which is determined by option. this timer is designed to prevent a software mal - function or sequence from jumping to an unknown loca - tion with unpredictable results. the watchdog timer can be disabled by options. if the watchdog timer is dis - abled, all the executions related to the wdt result in no operation. the rtc clock is enabled only in the internal rc+rtc mode. the wdt clock (f s ) is further divided by an internal counter to give longer watchdog time-outs. once the internal wdt oscillator (rc oscillator with a period of 65  s at 5v normally) is selected, it is first di - vided by 256 (8-stage) to get the nominal time-out pe - riod of approximately 17ms at 5v. this time-out period may vary with temperatures, vdd and process varia - tions. by invoking the wdt prescaler, longer time-out periods can be realized. writing data to ws2, ws1, ws0 (bit 2,1,0 of the wdts) can give different time-out periods. if ws2, ws1 and ws0 are all equal to  1  , the division ratio is up to 1:128, and the maximum time-out period is 2.1s at 5v seconds. if the wdt oscillator is dis - abled, the wdt clock may still come from the instruction clock and operate in the same manner except that in the halt state the wdt may stop counting and lose its pro- tecting purpose. in this situation the logic can only be re- started by external logic. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom- mended, since the halt will stop the system clock. bit no. label function 0~2 ws0~ ws2 wdt prescaler rate select 3~7  unused bit, read as  0  wdts (09h) register         
      
                
             ! " "                     
     system oscillator halt instruction clkmod rc oscillator 32768hz system clock mode during run state (halt not execute) 0 on on rc oscillator normal 1 off on 32768hz slow during run state (halt execute) x off on halt idle
ht48r01/HT48R02/ht48r03 rev. 1.00 13 december 20, 2006 ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 the wdt overflow under normal operation will initialise a
chip reset
and set the status bit
to
. but in the halt mode, the overflow will initialise a
warm reset
, and only the program counter and sp are reset to zero. to clear the contents of wdt (including the wdt prescaler), three methods are adopted; external reset (a low level to res), software instruction and a
halt
in- struction. the software instruction include
clr wdt
and the other set 
clr wdt1
and
clr wdt2
.of these two types of instruction, only one can be active de- pending on the option 
clr wdt times selection op- tion
.ifthe
clr wdt
is selected (i.e. clrwdt times equal one), any execution of the
clr wdt
instruction will clear the wdt. in the case that
clr wdt1
and
clr wdt2
are chosen (i.e. clrwdt times equal two), these two instructions must be executed to clear the wdt; otherwise, the wdt may reset the chip as a result of time-out. the wdt control register contains 4 bits of wdt enable bits. wdt can be enable by either wdt mask option or wdt control register (wdten[3:0]=0101b) and be dis - able by both being disable. bit no. label function 0~3 wdten0~ wdten3 bit3~0, wdten3~wdten0= 1010b: wdt disable others: enable (using 0101b to enable wdt is strongly recom - mended for the highest noise im - munity) 4~5  unused bit, read as
0
bit no. label function 6~7 intes0~ intes1 external interrupt edge selection (default=10) 00: disable 01: rising edge trigger 10: falling edge trigger 11: dual edge trigger wcon (17h) register power down operation  halt the halt mode is initialised by the
halt
instruction and results in the following...  the system oscillator will be turned off but the wdt oscillator keeps running (if the wdt oscillator is se - lected).  the contents of the on chip ram and registers remain unchanged.  wdt and wdt prescaler will be cleared and re- counted again (if the wdt clock is from the wdt os- cillator).  all of the i/o ports maintain their original status.  the pdf flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig - nal on port a or a wdt overflow. an external reset causes a device initialisation and the wdt overflow per - forms a
warm reset
. after the to and pdf flags are examined, the reason for chip reset can be determined. the pdf flag is cleared by system power-up or execut - ing the
clr wdt
instruction and is set when execut - ing the
halt
instruction. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer; the others keep their original status. both port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by options. awakening from an i/o port stimulus, the program will resume execution of the next instruc - tion. if it is awakened by an interrupt, two sequences may happen. if the related interrupt is disabled or the in - terrupt is enabled but the stack is full, the program will resume execution at the next instruction. if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. if an interrupt request flag is set to 5 : ?   '
      -   '      *   3 : ?   '
      5 :   : '   -   '     :    - 0 d -  
 !        $ 1  2 $  
-   
$ watchdog timer
ht48r01/HT48R02/ht48r03 rev. 1.00 14 december 20, 2006
1
before entering the halt mode, the wake-up func - tion of the related interrupt will be disabled. once a wake-up event occurs, it takes 1024 t sys (system clock period) to resume normal operation. in other words, a dummy period will be inserted after wake-up. if the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. if the wake-up results in the next in - struction execution, this will be executed immediately after the dummy period is finished. to minimise power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset can occur:  res reset during normal operation  res reset during halt  wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a
warm re - set
that resets only the program counter and sp, leav - ing the other circuits in their original state. some regis - ters remain unchanged during other reset conditions. most registers are reset to the
initial condition
when the reset conditions are met. by examining the pdf and to flags, the program can distinguish between different
chip resets
. to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note:
u
means
unchanged
to guarantee that the system oscillator is started and stabilised, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys - tem reset (power-up, wdt time-out or res reset) or the system awakes from the halt state. when a system reset occurs, the sst delay is added during the reset period. any wake-up from halt will en - able the sst delay. an extra option load time delay is added during a system reset (power-up, wdt time-out during normal mode or res reset). the functional unit chip reset status are shown below. program counter 000h interrupt disable prescaler clear wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack  , (   0 0 <  0 <  0 e  6 f 0 e 0  6 f reset circuit note:
*
make the length of the wiring, which is con- nected to the res pin as short as possible, to avoid noise interference. -    '     -   b  " 
 * !      ,     '      0 : ?   '     * 
      
reset configuration    , (    '     :   
#   ' '     reset timing chart
ht48r01/HT48R02/ht48r03 rev. 1.00 15 december 20, 2006 the register states are summarised in the following table. register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* program counter 000h 000h 000h 000h 000h mp0 (ht48r01/02) 1xxx xxxx 1uuu uuuu -uuu uuuu -uuu uuuu 1uuu uuuu mp1 (ht48r01/02) 1xxx xxxx 1uuu uuuu -uuu uuuu -uuu uuuu 1uuu uuuu mp0 (ht48r03) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 (ht48r03) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu wdts ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 (ht48r01) --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu intc0 (HT48R02/03) -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmr0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 0000 1000 0000 1000 0000 1000 0000 1000 uuuu uuuu tmr1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu papu -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu pawk -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu ctrl -0-- 0000 -0-- 0000 -0-- 0000 -0-- 0000 -u-- uuuu wcon 10-- 1010 10-- 1010 10-- 1010 10-- 1010 uu-- uuuu note:
*
means
warm reset

-
not implement
u
means
unchanged

x
means
unknown

ht48r01/HT48R02/ht48r03 rev. 1.00 16 december 20, 2006 timer/event counter one or two timer/event counters are implemented in the microcontroller. the timer/event counter contains an 8-bit programmable count-up counter and the clock may come from an external source, the system clock or rtc clock. using an external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base, while using the inter - nal clock allows the user to generate an accurate time base. the timer/event counter can generate a buzzer signal by using an external or internal clock. there are 2 registers related to the timer/event counter; tmr0 [0dh], tmr0c [0eh] (tmr1 [10h]), tmr1c [11h]). two physical registers are mapped to the tmr lo - cation; writing tmr0 (tmr1) places the start value into the timer/event counter preload register while reading tmr0 (tmr1) retrieves the contents of the timer/event counter. the tmr0c (tmr1c) is a timer/ event counter control register, which defines some options. the t0m0, t0m1 (t1m0, t1m1) bits define the operat - ing mode. the event count mode is used to count exter - nal events, which means the clock source comes from an external tmr0 (tmr1) pin. the timer mode func - tions as a normal timer with the clock source coming from the f int clock. the pulse width measurement mode can be used to count the high or low level duration of the external signal tmr0 (tmr1). the counting is based on the f int clock. in the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to ffh. once an overflow occurs, the counter is reloaded from the timer/event counter preload register and generates an interrupt request flag (t0f; bit 5 of intc0 or t1f bit 6 of intc0) at the same time. in the pulse width measurement mode with the values of t0on and t0e ( t1on and t1e) equal to 1, after the tmr0 (tmr1) has received a low to high transient (or high to low if t0e (t1e) is
0
), it will start counting until tmr0 (tmr1) returns to its original level and resets t0on (t1on). the measured result remains in the timer/event counter even if the activated transient oc - curs again. in other words, only a single cycle measure - ment can be implemented. not until the t0on (t1on) bit has been set again, will the cycle measurement func - tion again as long as it receives further transient pulses. note that, in this operating mode, the timer/event coun - ter starts counting not according to the logic level but ac - cording to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. to enable the counting op - eration, the timer on bit, t0on (t1on) should be set to 1. in the pulse width measurement mode, the t0on (t1on) will be cleared automatically after the measure- ment cycle is completed. but in the other two modes the t0on (t1on) can only be reset by instructions. the overflow of the timer/event counter is one of the wake-up sources. no matter what the operation mode is, writin ga0toetican disable the interrupt service.  0  0 0   0  0 ,  0  0 0  0     *  ' -  !  #           !  '
     * 5 : ?   '       , =    '
         *   ! '        5 : ?   '       , =   
      ' 0 ' 7   0 8     ' .    *   !  =   $ *  @   '          3 :     '      *   5 : '   $ 1 $     0 
d  0 
0    
' 
 0 $    . / 0 timer/event counter 0   0    ,   0      *  ' -  !  #           !  '
     * 5 : ?   '       , =    '
         *   ! '        5 : ?   '       , =   
      ' ' 7   8     ' .    *   !  =   $ *  @   '          $ 1  2    
' 
  . / timer/event counte r 1 - HT48R02/ht48r03 only
ht48r01/HT48R02/ht48r03 rev. 1.00 17 december 20, 2006 bit no. label function 0~2 t0psc0~ t0psc2 to define the prescaler stages, t0psc2, t0psc1, t0psc0= 000: f int =f tp 001: f int =f tp /2 010: f int =f tp /4 011: f int =f tp /8 100: f int =f tp /16 101: f int =f tp /32 110: f int =f tp /64 111: f int =f tp /128 3 t0e to define the tmr active edge of the timer/event counter in event counter mode (t0m1,t0m0)=(0,1): 1: count on falling edge 0: count on rising edge in pulse width measurement mode (t0m1,t0m0)=(1,1): 1: start counting on rising edge, stop on falling edge 0: start counting on falling edge, stop on rising edge 4 t0on to enable or disable timer counting (0=disabled; 1=enabled) 5 t0s timer clock source selection 0: f sys 1: rtc 6 7 t0m0 t0m1 to define the operating mode (t0m1, t0m0) 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr0c (0eh) register in the case of timer/event counter off condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. but if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. the timer/event counter will still operate until overflow occurs. when the timer/event counter is read, the clock will be blocked to avoid errors. as clock blocking may re - sults in a counting error, this must be taken into consid - eration by the programmer. the bit 0~2 of the tmr0c can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. the definitions are as shown. the timer/event counter overflow signals can be used to generate signals for the buzzer. bit no. label function 0~2  unused bit, read as
0
3 t1e to define the tmr active edge of the timer/event counter in event counter mode (t1m1,t1m0)=(0,1): 1: count on falling edge 0: count on rising edge in pulse width measurement mode (t1m1,t1m0)=(1,1): 1: start counting on rising edge, stop on falling edge 0: start counting on falling edge, stop on rising edge 4 t1on to enable or disable timer counting (0=disabled; 1=enabled) 5 t1s timer clock source selection 0: f sys /4 1: rtc 6 7 t1m0 t1m1 to define the operating mode (t1m1, t1m0) 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr1c (11h) register
ht48r01/HT48R02/ht48r03 rev. 1.00 18 december 20, 2006 input/output ports there are 7 bi-directional input/output lines and 1 input line in the microcontroller, labeled as pa, which are mapped to the data memory of [12h]. all of the i/o ports can be used for input or output operations. for input op - eration, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction
mov a,[m]
(m=12h). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac) to control the input/output configuration (pa7 for input only). with this control register, a cmos output or schmitt trigger input ( with or without pull-high resistor structures) can be reconfigured dynamically (i.e. on-the-fly) under software control ( the pa7 only provide input mode). to function as an input, the corresponding latch of the control register must write
1
. the input source also depends on the control register. if the con - trol register bit is
1
, the input will read the pad state. if the control register bit is
0
, the contents of the latches will move to the internal bus. the latter is possible in the
read-modify-write
instruction. for output function, cmos is the only configuration. these control register is mapped to locations 13h. after a chip reset, these in - put/output lines remain at high levels or floating state (dependent on pull-high options). each bit of these in- put/output latches can be set or cleared by
set [m].i

clr [m].i
(m=12h) instructions. some instruc - tions first input data and then follow the output opera - tions. for example,
set [m].i
,
clr [m].i
,
cpl [m]
,
cpla [m]
read the entire port states into the cpu, ex - ecute the defined operations (bit-operation), and then write the results back to the latches or the accumulator.  wake up and pull-high function each line (except pa7) of pa port supports waking-up mcu and pull-high function which are controlled by pawk, papu registers respectively. pa7 hasn  t wake-up and pull-high function. bit no. label function 0~6 pawk0~ pawk6 pawkn= 0, pan wake-up is dis - able pawkn=1, pan wake-up is en - able 7  unused bit, read as
0
pawk (15h) register bit no. label function 0~6 papu0~ papu6 papun= 0, pan pull-up is disable papun=1, pan pull-up is enable 7  unused bit, read as
0
papu (14h) register (       . / ,  ' 7   0    8
     * ' .       ' .  -     '
     * '       
#   '        ! '
     * '        -     '     '            ' .    g
 g  g
 g   0  . /    . /      0          2      )  
  +  
  ' $   '   '   *     ' $   '    '   *      ' -  <  :   ' 7   0 d   + '   *  8    ! '     '        7   & '   0 8 7 . / & ' . / 8   -  + d   -  0     + d     0 input/output ports (pa0~pa6)    ! '         ' .   , ' $   '   3 '   *    3 input/output ports (pa7)
ht48r01/HT48R02/ht48r03 rev. 1.00 19 december 20, 2006  buzzer function pa0 and pa1 are pin-shared with the bz and bz buzzer signals, respectively. if the buzzer option is se - lected, then if these pins are setup as outputs, the sig - nals on pa0 (or pa1) will be the buzzer signal. if setup as inputs, they will always retain their original input functions. the buzzer output signals (in output mode) are con - trolled by the pa0 data register only. the truth table for pa0/bz and pa1/bz are listed below. port a also has a cmos or schmitt trigger input configuration option (all port a i/o lines are controlled by a option bit). the truth table for pa0/bz and pa1/bz is as shown. pa0i/o iiiiooo ooooo pa1i/o i ooo i i i ooooo pa0 mode xxxxcbbc bbbb pa1 mode x c b b x x x c c c b b pa0 data x x 0 1 d 0 1 d 0 0101 pa1 data x d xxxxxd 1 dd x x pa0 pad status iiiid0bd 0 0b0b pa1 pad status i d 0 b i i i d 1 dd0 b note: i: input; o: output; d, d 0 ,d 1 : data; b: buzzer option, bz or bz ; x: don't care c: cmos output low voltage reset  lvr the microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr , such as when changing the battery, the lvr will automatically reset the device internally. the lvr includes the following specifications:  the low voltage (0.9v~v lvr ) has to remain in this con - dition for a time greater than 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and will not perform a reset function.  the lvr uses an
or
function with the external res signal to perform a chip reset. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip opera- tion with a 4mhz system clock. ) e ) ( e ( e ( 0 e 4 ( (   (    ( " (  ) e ) ( ) e ) (  e ) ( e ( 0 e 4 ( (   (    ( " (  ) e ) ( ) e ) ( 2 e ( e ( 0 e 4 ( (   (    ( " (  ) e ) ( (   ) e ) ( ( " (  0 e 4 ( 0 (     '     *     f f      * '              " (  '       ' (  *     low voltage reset note: *1: to make sure that the system oscillator has stabilised, the sst provides an extra delay of 1024 system clock pulses before entering normal operation. *2: since the low voltage has to be maintained in its original state and exceed t lvr , therefore a t lvr delay enters the reset mode.
ht48r01/HT48R02/ht48r03 rev. 1.00 20 december 20, 2006 configuration options the following table shows the various configuration options for the microcontroller. all options must be defined for proper system functioning. items options 1 system oscillator selection  internal rc + pa5/pa6  internal rc + rtc  external xtal  external rc + pa5 2 internal rc frequency selection: 4mhz, 8mhz or 12mhz 3 wdt function: enable or disable 4 wdt clock source: wdtosc, f sys /4 or rtc osc 5 clrwdt instruction(s): one or two clear wdt instruction(s) 6 lvr function: enable or disable 7 lvr selection: 2.1v/3.15v/4.2v 8 res or pa7 input selection
application circuits note: the resistance and capacitance for the reset circuit should be designed to ensure that vdd is stable and remains in a valid range of the operating voltage before bringing res high.
*
make the length of the wiring, which is connected to the res pin as short as possible, to avoid noise interference. the following table shows the c1, c2 and r1 values corresponding to the different crystal values. (for refer- ence only) crystal or resonator c1, c2 r1 8mhz crystal & resonator 35pf 3.9k 4mhz crystal 10pf 10k 4mhz resonator 10pf 12k 3.58mhz crystal 10pf 12k 3.58mhz resonator 10pf 12k 2mhz crystal & resonator 35pf 12k 1mhz crystal 68pf 18k 480khz resonator 300pf 10k 455khz resonator 300pf 10k 429khz resonator 300pf 10k 400khz resonator 300pf 10k the function of the resistor r1 is to ensure that the oscillator will switch off should low voltage condi - tions occur. such a low voltage, as mentioned here, is one which is less than the lowest value of the mcu operating voltage. note however that if the lvr is enabled then r1 can be removed. ht48r01/HT48R02/ht48r03 rev. 1.00 21 december 20, 2006                        

       
               6   '
& '
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h e )  (    

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  )   + 
0  6  3 + 5 b > 

instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none ht48r01/HT48R02/ht48r03 rev. 1.00 22 december 20, 2006
mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh (this instruction is not valid for ht48r05a-1/ht48c05) 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pdf to (4) ,pdf (4) to (4) ,pdf (4) none none to,pdf note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address  : flag is affected  : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the
clr wdt1
or
clr wdt2
instruction, the to and pdf are cleared. otherwise the to and pdf flags remain unchanged. ht48r01/HT48R02/ht48r03 rev. 1.00 23 december 20, 2006
instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc  acc+[m]+c affected flag(s) to pdf ov z ac c  adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m]  acc+[m]+c affected flag(s) to pdf ov z ac c  add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc  acc+[m] affected flag(s) to pdf ov z ac c  add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc  acc+x affected flag(s) to pdf ov z ac c  addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m]  acc+[m] affected flag(s) to pdf ov z ac c  ht48r01/HT48R02/ht48r03 rev. 1.00 24 december 20, 2006
and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc  acc
and
[m] affected flag(s) to pdf ov z ac c  and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc  acc
and
x affected flag(s) to pdf ov z ac c  andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m]  acc
and
[m] affected flag(s) to pdf ov z ac c  call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack  program counter+1 program counter  addr affected flag(s) to pdf ov z ac c  clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m]  00h affected flag(s) to pdf ov z ac c  ht48r01/HT48R02/ht48r03 rev. 1.00 25 december 20, 2006
clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i  0 affected flag(s) to pdf ov z ac c  clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pdf) and time-out bit (to) are cleared. operation wdt  00h pdf and to  0 affected flag(s) to pdf ov z ac c 00  clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt  00h* pdf and to  0* affected flag(s) to pdf ov z ac c 0* 0*  clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which im - plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt  00h* pdf and to  0* affected flag(s) to pdf ov z ac c 0* 0*  cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1  s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m]  [m ] affected flag(s) to pdf ov z ac c  ht48r01/HT48R02/ht48r03 rev. 1.00 26 december 20, 2006
cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1  s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc  [m ] affected flag(s) to pdf ov z ac c  daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0  (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0  (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4  acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4  acc.7~acc.4+ac1,c=c affected flag(s) to pdf ov z ac c   dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m]  [m]  1 affected flag(s) to pdf ov z ac c  deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc  [m]  1 affected flag(s) to pdf ov z ac c  ht48r01/HT48R02/ht48r03 rev. 1.00 27 december 20, 2006
halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pdf) is set and the wdt time-out bit (to) is cleared. operation program counter  program counter+1 pdf  1 to  0 affected flag(s) to pdf ov z ac c 01  inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m]  [m]+1 affected flag(s) to pdf ov z ac c  inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc  [m]+1 affected flag(s) to pdf ov z ac c  jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation program counter  addr affected flag(s) to pdf ov z ac c  mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc  [m] affected flag(s) to pdf ov z ac c  ht48r01/HT48R02/ht48r03 rev. 1.00 28 december 20, 2006
mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc  x affected flag(s) to pdf ov z ac c  mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m]  acc affected flag(s) to pdf ov z ac c  nop no operation description no operation is performed. execution continues with the next instruction. operation program counter  program counter+1 affected flag(s) to pdf ov z ac c  or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc  acc
or
[m] affected flag(s) to pdf ov z ac c  or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc  acc
or
x affected flag(s) to pdf ov z ac c  orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m]  acc
or
[m] affected flag(s) to pdf ov z ac c  ht48r01/HT48R02/ht48r03 rev. 1.00 29 december 20, 2006
ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation program counter  stack affected flag(s) to pdf ov z ac c  ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation program counter  stack acc  x affected flag(s) to pdf ov z ac c  reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation program counter  stack emi  1 affected flag(s) to pdf ov z ac c  rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1)  [m].i; [m].i:bit i of the data memory (i=0~6) [m].0  [m].7 affected flag(s) to pdf ov z ac c  rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1)  [m].i; [m].i:bit i of the data memory (i=0~6) acc.0  [m].7 affected flag(s) to pdf ov z ac c  ht48r01/HT48R02/ht48r03 rev. 1.00 30 december 20, 2006
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1)  [m].i; [m].i:bit i of the data memory (i=0~6) [m].0  c c  [m].7 affected flag(s) to pdf ov z ac c   rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1)  [m].i; [m].i:bit i of the data memory (i=0~6) acc.0  c c  [m].7 affected flag(s) to pdf ov z ac c   rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i  [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7  [m].0 affected flag(s) to pdf ov z ac c  rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i)  [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7  [m].0 affected flag(s) to pdf ov z ac c  rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i  [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7  c c  [m].0 affected flag(s) to pdf ov z ac c   ht48r01/HT48R02/ht48r03 rev. 1.00 31 december 20, 2006
rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i  [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7  c c  [m].0 affected flag(s) to pdf ov z ac c   sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc  acc+[m ]+c affected flag(s) to pdf ov z ac c  sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m]  acc+[m ]+c affected flag(s) to pdf ov z ac c  sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]  1)=0, [m]  ([m]  1) affected flag(s) to pdf ov z ac c  sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]  1)=0, acc  ([m]  1) affected flag(s) to pdf ov z ac c  ht48r01/HT48R02/ht48r03 rev. 1.00 32 december 20, 2006
set [m] set data memory description each bit of the specified data memory is set to 1. operation [m]  ffh affected flag(s) to pdf ov z ac c  set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i  1 affected flag(s) to pdf ov z ac c  siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m]  ([m]+1) affected flag(s) to pdf ov z ac c  siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc  ([m]+1) affected flag(s) to pdf ov z ac c  snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i  0 affected flag(s) to pdf ov z ac c  ht48r01/HT48R02/ht48r03 rev. 1.00 33 december 20, 2006
sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc  acc+[m ]+1 affected flag(s) to pdf ov z ac c  subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m]  acc+[m ]+1 affected flag(s) to pdf ov z ac c  sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc  acc+x +1 affected flag(s) to pdf ov z ac c  swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0  [m].7~[m].4 affected flag(s) to pdf ov z ac c  swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0  [m].7~[m].4 acc.7~acc.4  [m].3~[m].0 affected flag(s) to pdf ov z ac c  ht48r01/HT48R02/ht48r03 rev. 1.00 34 december 20, 2006
sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c  sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c  sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) to pdf ov z ac c  tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m]  rom code (low byte) tblh  rom code (high byte) affected flag(s) to pdf ov z ac c  tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer ( tblp ) is moved to the data memory and the high byte transferred to tblh directly. note that this instruction is not valid for ht48r05a-1/ht48c05 operation [m]  rom code (low byte) tblh  rom code (high byte) affected flag(s) to pdf ov z ac c  ht48r01/HT48R02/ht48r03 rev. 1.00 35 december 20, 2006
xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc  acc
xor
[m] affected flag(s) to pdf ov z ac c  xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m]  acc
xor
[m] affected flag(s) to pdf ov z ac c  xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc  acc
xor
x affected flag(s) to pdf ov z ac c  ht48r01/HT48R02/ht48r03 rev. 1.00 36 december 20, 2006
package information 10-pin msop outline dimensions symbol dimensions in mm min. nom. max. a  1.1 a1 0  0.15 a2 0.75  0.95 b 0.17  0.27 c  0.25 d  3  e  4.9  e1  3  e  0.5  l 0.4  0.8 l1  0.95   0  8  ht48r01/HT48R02/ht48r03 rev. 1.00 37 december 20, 2006   ,  .   ' 0 e 0 7 2 '
   ,  8 " ,
  ) + 0 "
ht48r01/HT48R02/ht48r03 rev. 1.00 38 december 20, 2006 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 86-21-6485-5560 fax: 86-21-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5/f, unit a, productivity building, cross of science m 3rd road and gaoxin m 2nd road, science park, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9533 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holmate semiconductor, inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holmate.com copyright  2006 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek  s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.


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